ti memory management units (MMUs)

A memory management unit (MMU) is a hardware component responsible for handling accesses to memory requested by a processing unit, DMA controller, or other bus requestor. MMU functions include:

• Translation of initiator internal (virtual) addresses to physical addresses (that is, virtual memory management)
• Preventing an initiator from making accesses to unmapped pages of the system memory

Two major functional units exist in the MMU to provide address translation automatically based on the table entries:

• The table walker automatically retrieves the correct translation table entry for a requested translation. If two-level translation is used (for the translation of small memory pages), the table walker also automatically reads the required second-level translation table entry. The two-level translation is described later in the chapter.

• The translation look-aside buffer (TLB) stores recently used translation entries, acting like a cache of the translation table.

Translation tables

ti tda3 (tda3ma, tda3md, tda3mv, tda3la):
1) datasheet
2) trm

3) dm505 datasheet

arm cortex-m4:
1) trm
2) generic user guide