9.1 Display Subsystem Overview
The Display Subsystem (DSS) provides the logic to interface display peripherals. DSS integrates a DMA engine as part of DISPC module, which allows direct access to the memory frame buffer. Various pixel processing capabilities are supported, such as: color space conversion, filtering, scaling, blending, color keying, etc.
The supported display interfaces are:
• One parallel CMOS output, which can be used for MIPI® DPI 2.0, or BT-656 or BT-1120.
• One TV output, which is connected to the internal Video Encoder module (VENC). The VENC drives a single video digital-to-analog converter (SD_DAC) supporting composite video mode.
The modules integrated in the display subsystem are:
• Display controller (DISPC), with the following main features
– One direct memory access (DMA) engine
– One graphics pipeline (GFX), two video pipelines (VID1 and VID2), and one write-back pipeline
(WB)
– Two overlay managers
– Active Matrix color support for 12/16/18/24-bit (truncated or dithered encoded pixel values)
– One Video Port (VP) with programmable timing generator to support:
• DPI: up to 165 MHz pixel clock video formats defined in CEA-861-E and VESA DMT standards
• VENC: NTSC/PAL standards with 60Hz/50Hz refresh rates
– Supported maximum FrameBuffer width of 4096 for all pixel formats
– Configurable output mode: progressive or interlaced
– Selection between RGB and YUV422 output pixel formats (YUV4:2:2 only available when BT-656
or BT-1120 output mode is enabled)
– Refer to Section 9.2, Display Controller, for more details
• Video Encoder (VENC) with 10-bit standard definition video DAC (SD_DAC). Refer to Section 9.3,
Video Encoder, for more details.
DSS provides two interfaces to L3_MAIN interconnect
• One 128-bit master port (with MFLAG support). The DMA engine in DISPC uses this single master to read/write data from/to device system memory.
• One 32-bit slave port. Used for registers configuration. It is further connected internally to DISPC and
VENC modules.
Figure 9-1 is a high-level diagram of the display subsystem.
9.1.1 Display Subsystem Environment
This section describes the various outputs handled by the display subsystem:
• Parallel interface (MIPI DPI 2.0, or BT-656 or BT-1120) support
• TV (composite video) output support
Figure 9-2 is a diagram of the display subsystem environment.
9.1.2 Display Subsystem Integration
This section describes the integration of the display subsystem module in the device, including information about clocks, resets, and hardware requests.
Figure 9-3 shows the integration of the display subsystem in the device.
9.1.2.2 Display Subsystem Clocks
The power, reset, and clock management (PRCM) module provides the clock signals, and status for their activity, to the display subsystem.
Figure 9-4 shows the details of the display subsystem clock tree.
9.2 Display Controller
9.2.1 DISPC Overview
The DISPC includes the following main features:
• Pipelines for processing:
– One Graphics (GFX) pipeline:
• Pixel formats: ARGB16-4444, ABGR16-4444, RGBA16-4444, RGB16-565, BGR16-565,
ARGB16-1555, ABGR16-1555, ARGB32-8888, ABGR32-8888, BGRA32-8888, RGBA32-8888,
RGB24-888, ARGB32-2101010, ABGR32-2101010, ARGB48-12121212, RGBA48-12121212,
ARGB64-16161616, RGBA64-16161616, BITMAP1, BITMAP2, BITMAP4, BITMAP8. (A
component can be ignored by not selecting Alpha pixel)
• Premultiplied ARGB and RGBA formats
• Selection of the color depth expansion from ARGB16-4444, RGBA16-4444, and ARGB16-1555
to ARGB32-8888, and from xRGB12-4444, RGBx12-4444, and xRGB16-1555 to xRGB32-8888
(replication of the most significant bits [MSBs])
• Support for color look-up table (CLUT): 256 × 24-bit entries palette in RGB
• Support for anti-aliasing on RGB pixel formats using 3-tap filter
• Up to 4K-by-4K frame buffer size
– Two Video pipelines (VID1 and VID2):
• Pixel formats: ARGB16-4444, ABGR16-4444, RGBA16-4444, RGB16-565, BGR16-565,
ARGB16-1555, ABGR16-1555, ARGB32-8888, ABGR32-8888, BGRA32-8888, RGBA32-8888,
RGB24-888, ARGB32-2101010, ABGR32-2101010, ARGB48-12121212, RGBA48-12121212,
ARGB64-16161616, RGBA64-16161616, RGB565-A8, BITMAP1, BITMAP2, BITMAP4,
BITMAP8, YUV422-UYVY, YUV422-YUV2, YUV420-NV12, YUV420-NV21 and in addition
RGBx, xRGB, xBGR, and BGRx pixel formats defined considering that A component of RGBA,
ARGB, ABGR, BGRA pixel formats is ignored by HW (e.g. ARGB->xRGB)
• Premultiplied ARGB and RGBA formats
• Support for color look-up table (CLUT): 256 × 24-bit entries palette in RGB
• Programmable poly-phase filter:
• Independent horizontal and vertical resampling. Upsampling up to x16, and downsampling
down to 1/4
• Maximum input width of 1280 pixels (2560 in 3-tap mode)
• No limitation on the input height
• Supported input formats are all above listed formats, except BITMAP formats. The alpha
blending factor is rescaled like the R, G and B color components. 16 phases with
symmetrical coefficients are implemented.
• Programmable color space conversion from YUV4:2:2 (YUV4:4:4, YUV4:2:0 after Chroma
upsampling through the scaler) into ARGB48-12121212.
• Programmable VC-1 range mapping
• Up to 4K-by-4K frame buffer size
– One Write-back (WB) pipeline: Allows the use of the hardware processing available inside the
DISPC, such as color space conversion, rescaling, and compositing to perform memory-to-memory
transfer with data processing or capturing a displayed frame
• Pixel formats: ARGB16-4444, ABGR16-4444, RGBA16-4444, RGB16-565, BGR16-565,
ARGB16-1555, ABGR16-1555, ARGB32-8888, ABGR32-8888, BGRA32-8888, RGBA32-8888,
RGB24-888, ARGB32-2101010, ABGR32-2101010, ARGB48-12121212, RGBA48-12121212,
ARGB64-16161616, RGBA64-16161616, RGB565-A8, YUV422-UYVY, YUV422-YUV2,
YUV420-NV12, YUV420-NV21 and in addition RGBx, xRGB, xBGR, and BGRx pixel formats
defined considering that A component of RGBA, ARGB, ABGR, BGRA pixel formats is ignored
by HW (e.g. ARGB->xRGB)
• Programmable color space conversion RGB24 into YUV4:2:2-UYVY, YUV4:2:2-YUV2,
YUV4:2:0-NV12, or YUV4:2:0-NV21
• Programmable poly-phase filter:
• Independent horizontal and vertical resampling. Upsampling up to x16, and downsampling
down to 1/4. When the output format of WB pipeline includes a format change from RGB or
YUV4:2:2 to YUV4:2:0, the maximum downscaling provided by the WB scaler is 1/2.
• Maximum input width of 1280 pixels using 32-bit pixels and 5-tap, and 2560 pixels using 32-
bit pixels and 3-tap
• No limitation on the input height
• The supported formats are RGB888/RGBA-8888/ARGB32-8888, ARGB48-12121212,
RGB565-A8, YUV422-UYVY, YUV422-YUV2, YUV420-NV12 and YUV420-NV21
• Alpha blending factor is rescaled like the R, G, and B color components
• 16 phases with symmetrical coefficients are implemented
• Selection of the source of the data:
• One of the overlay manager outputs
• One of the pipeline outputs
• One Video Port (VP1) output:
– Up to 24-bit per pixel on the output interface, with selection between 12, 16, 18 or 24-bit
– Independent programmable timing generator to support up to 165 MHz pixel clock video formats
defined in CEA-861-E and VESA-DMT standards
– Independent programmable multiple cycles output format on 8/9/12/16-bit interface (TDM)
– Configurable output mode: progressive or interlaced mode
– Selection between RGB and YUV422 output pixel format ( YUV4:2:2 only available when BT output
is enabled)
• Two Overlay Managers (OVR1 and OVR2):
– Input Pixel format: ARGB48-12121212
– Output Pixel format: ARGB48-12121212 (A component is only used for Write-back)
– Overlay of the graphics and video pipelines
– Transparency color keys (source and destination)
– Global and pixel alpha blending
– Programmable Z-order (full flexibility)
• Common:
– Programmable 8-bit gamma curve support on VP1 output
– Programmable color phase rotation (CPR)
– Alpha blending support:
• Embedded pixel factor (ARGB and RGBA)
• Global pixel
• Combination of global pixel and pixel factor
• DMA (internal to the DISPC):
– No support for rotation, flip-flop, mirroring and memory fragmentation
– Integrated shared buffers between DMA engine and pipelines
– Programmable buffer thresholds
– Bandwidth limiter on write request (insertion on idle cycles between requests)
• Advanced:
– Mode outputting data on display only from the DMA buffer (self-refresh using the DMA FIFO)
– Arbitration between normal and low priority pipelines (GFX, VID1, VID2 and WB pipelines)
• Power modes:
– Low-power saving modes
– Support on-the-fly dynamic voltage and frequency scaling (DVFS)
– Merge capability of the DMA buffers to support greater OFF period on the L3_MAIN interconnect
• All buffers associated to a single pipeline
• Reallocation of the buffers of the nonactive pipelines to the active pipelines
The DISPC can read and display the encoded pixel data stored in memory and write the output of one of the overlays or one of the pipelines into system memory.
Several processes can be configured to manage the graphics pipeline (antialiasing) and video pipelines
(VC-1, color space conversion, scaling, and so forth).
The data coming out of a pipeline is sent to the overlay managers (and from there to VP1 or WB), or to
the WB pipeline directly. An overlay manager manages inputs of multiple pipelines. Transparency settings and user timing configurations for VP1 output are available, based on VESA-DMT and CEA-861 standards.
The DISPC allows the capturing of one of the pipeline outputs, or one of the overlay manager outputs, to redirect it into the WB pipeline. It allows the use of the hardware processing available inside the DISPC, such as color space conversion, rescaling, and compositing, and so forth, to perform memory-to-memory transfer with data processing. It can be used as a HW front end compositing unit in order to pre-compose the output frame and write in memory before being fetched again by DISPC for display on VP1.
NOTE: DISPC does not support any tiled frame buffer, nor any compressed frame buffer, and is not
able to generate any compressed output to memory through the write-back pipeline. The DISPC has no capability to support by itself rotation of the frame buffer.
DISPC can be used for composition using memory to memory transfer. In that case the frame buffer on the input and output can be split into smaller blocks of pixels, processed separately by DISPC. Scaling/filtering of the split blocks requires fetching extra pixels around the processed pixel-block. This can be achieved by properly programming the initial accumulator (accu) value of the polyphase filter inside VID/WB pipelines. The number of taps used by the polyphase filter implies the number of extra pixels to fetch (5-tap requires 2 pixels on left/right/bottom/top to be fetched).
BT-656:
2) Особенности применения протокола цифровой передачи видео данных ITU-R BT.656 при разработке запоминающего устройства записи видеоинформации https://moluch.ru/archive/159/44866/
BT-1120:
7) Implementation of High-Speed 512-Tap FIR Filters for Chromatic Dispersion Compensation http://liu.diva-portal.org/smash/get/diva2:1271001/FULLTEXT01.pdf
9) Implementing FIR Filters in FLEX Devices http://www.ee.ic.ac.uk/pcheung/teaching/ee3_dsd/fir.pdf
Алгоритмы wdrc, dde:
1) dde (digital detail enhancement) https://www.flirmedia.com/MMC/CVS/Tech_Notes/TN_0003_EN.pdf
7) fft-based dynamic range compression http://smc2017.aalto.fi/media/materials/proceedings/SMC17_p42.pdf
bt.656:
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