tda3x timer

18.1 Timers Overview

The device includes several types of timers used by the system software, including eight general-purpose (GP) timers, and a 32-kHz synchronized timer (COUNTER_32K). Figure 18-1 shows a high-level block diagram of the device timers.

The 32-kHz sync timer, which is reset only at power up, provides the operating system (OS) with a stable timing source that stores the relative time since the last power cycle of the product. The eight GP timers, which are useful as basic timers, are included to generate time-stamp-based interrupts to the system software or to use as a source of pulse-width modulation (PWM) signals.

18.2 General-Purpose Timers

18.2.1 General-Purpose Timers Overview

The device has eight GP timers: TIMER1 through TIMER8.

• TIMER1 (1-ms tick) includes a specific function to generate accurate tick interrupts to the operating

system and it belongs to the PD_WKUPAON domain.

• TIMER2 through TIMER8 belong to the PD_COREAON module.

Each timer can be clocked from the system clock (19.2, 20, or 27 MHz) or the 32-kHz clock. Select the

clock source at the power, reset, and clock management (PRCM) module level.

Each timer provides an interrupt through the device IRQ_CROSSBAR.

Each timer is connected to an external pin by their PWM output or their event capture input pin (for

external timer triggering). Figure 18-2 shows an overview of the GP timers.

18.2.1.1 GP Timer Features

The following are the main features of the GP timer controllers:

• Level 4 (L4) slave interface support:

– 32-bit data bus width

– 32- or 16-bit access supported

– 8-bit access not supported

– 10-bit address bus width

– Burst mode not supported

– Write nonposted transaction mode supported

• Interrupts generated on overflow, compare, and capture

• Free-running 32-bit upward counter

• Compare and capture modes

• Autoreload mode

• Start and stop mode

• Programmable divider clock source (2n, where n = [0:8])

• Dedicated input trigger for capture mode and dedicated output trigger/PWM signal

• Dedicated GP output signal for using the TIMERi_GPO_CFG signal

• On-the-fly read/write register (while counting)

• 1-ms tick with 32.768-Hz functional clock generated (only TIMER1)

18.2.2 GP Timer Environment

18.2.2.1 GP Timer External System Interface

Each timer can send or receive stimulus to and from the external (off-chip) system. In the device all timers are configured to output a PWM pulse or receive an external event signal used as a trigger to capture the current timer count. Figure 18-3 shows the external system interface for the GP timers, and Table 18-1 describes the GP timer inputs and outputs.

NOTE: Software control must ensure that MUX mode is configured to select the timeri (where i = 1

to 8) signal on only one pad. Other pads on which the same signal is multiplexed must be

configured in safe mode or non-dmtimer mode to avoid two different pads driving the same

signal. For more information about the configuration of the timeri I/O pads, see Section 14.4.6.1,

Pad Configuration Registers.

18.2.3 GP Timer Integration

Figure 18-4 shows the integration of the GP timer in the device.

Table 18-2 through Table 18-4 summarize the integration of the module in the device.

18.2.4 GP Timer Functional Description

Each GP timer contains a free-running upward counter with autoreload capability on overflow. The timer counter can be read and written on-the-fly (while counting). Each GP timer includes compare logic to allow an interrupt event on a programmable counter matching value. A dedicated output signal can be pulsed or toggled on either an overflow or a match event. This offers time-stamp trigger signaling or PWM signal sources. A dedicated input signal can be used to trigger an automatic timer counter capture or an interrupt event on a programmable input signal transition. A programmable clock divider (prescaler) allows reduction of the timer input clock frequency. All internal timer interrupt sources are merged into one module interrupt line and one wake-up line.

Each internal interrupt source can be independently enabled and disabled by a dedicated bit in the

IRQSTATUS_SET and IRQSTATUS_CLR registers for the interrupt features, and a dedicated bit of the

IRQWAKEEN register for the wake-up of TIMER1. In addition, a mechanism implemented in these timers generate an accurate tick interrupt. For all other internal interrupts, the source can be independently enabled and disabled through the IRQENABLE_SET and IRQENABLE_CLR registers.

For each GP timer implemented in the device, there are two possible clock sources:

• 32-kHz clock

• System clock

The input clock source is selected in the registers in the PRCM configuration (see Section 18.2.1, GP

Timer Overview). 

Each GP timer supports three functional modes:

• Timer mode

• Capture mode

• Compare mode

The capture and compare modes are disabled by default after core reset.

18.2.4.1 GP Timer Block Diagram

Figure 18-5 is a block diagram of the common GP timers, and Figure 18-6 is a block diagram of the GP

timers with a 1-ms tick generation module.