Uninteresting Build Notes: ti tda3 power, clock management system (prcm) and digital phase-locked loop (dpll) subsystem

Power and clock management system (presentation in pdf)

3.1 Device Power Management Introduction

Power management is one of the most important design aspects of any system.

The device power-management architecture ensures maximum performance while offering versatile
power-management techniques for maximum design flexibility, depending on application requirements.

This introduction contains the following information:

• Power-management architecture building blocks for the device

• State-of-the-art power-management techniques supported by the power-management architecture of

the device

3.1.1 Device Power-Management Architecture Building Blocks

To provide a versatile architecture that supports multiple power-management techniques, the powermanagement framework is built with three levels of resource management: clock, power, and voltage. These management levels are enforced by defining the managed entities or building blocks of the powermanagement architecture, called the clock, power, and voltage domains. A domain is a group of modules or subsections of the device that share a common entity (for example, common clock source, common voltage source, or common power switch). The group forming the domain

is managed by a policy manager. For example, a clock for a clock domain is managed by a dedicated

clock manager within the power, reset, and clock management (PRCM) module. The clock manager

considers the joint clocking constraints of all the modules belonging to that clock domain (and, hence,

receiving that clock).

NOTE: In the following sections, the term <module> is used to represent the device IPs (that is,

modules or subsystems), other than the PRCM module, that receive clock, reset, or power

signals from the PRCM module.

3.1.1.1 Clock Management

The PRCM module manages the gating (that is, switching off) and enabling of the clocks to the device

modules. The clocks are managed based on the requirement constraints of the associated modules. The

following sections identify the module clock characteristics, management policy, clock domains, and clock domain management. Clock management integration details are described in Section 3.6, Clock

Management Functional Description.

3.1.1.1.1 Module Interface and Functional Clocks

Each module within the device has specific clock input characteristics requirements. Based on the

characteristics of the clocks delivered to the modules, the clocks are divided into two categories: interface clocks and functional clocks (see Figure 3-2).

The interface clocks have the following characteristics:

• They ensure proper communication between any module/subsystem and the interconnect.

• In most cases, they supply the system interconnect interface and registers of the module.

• A typical module has one interface clock, but modules with multiple interface clocks may also exist

(that is, when connected to multiple interconnect buses).

• Interface clock management is done at the device level.

• From the standpoint of the PRCM module, an interface clock is identified with an _ICLK suffix.

Functional clocks have the following characteristics:

• They supply the functional part of a module or subsystem.

• A module can have one or more functional clocks. Some functional clocks are mandatory, while others

are optional. A module needs its mandatory clock(s) to be operational. The optional clocks are used for

specific features and can be shut down without stopping the module activity (for example, the clock for

the camera).

• From the standpoint of the PRCM module, a functional clock is distributed directly to the related

modules through a dedicated clock tree. It is identified with an _FCLK suffix.

Some clocks are qualified as permanent clocks. They are functional clocks, that can stay active while the corresponding entity manages them.

3.1.1.1.2 Module-Level Clock Management

Each module in the device may also have specific clock requirements. Certain module clocks must be

active when operating in specific modes, or they may be gated. Globally, the activation and gating of the module clocks are managed by the PRCM module. Hence, the PRCM module must be aware of when to activate and when to gate the module clocks.

The PRCM module differentiates the clock-management behavior for device modules based on whether

the module can initiate transactions on the device interconnect (called master module) or it cannot initiate transactions and only responds to the transactions initiated by the master (called slave module). Thus, two hardware-based power-management protocols are used:

• Master standby protocol: Clock-management protocol between the PRCM and master modules

• Slave idle protocol: Clock-management protocol between the PRCM and slave modules

<...>

Master module STANDBY and slave module IDLE protocols (from presentation).

3.1.1.1.3 Clock Domain

A clock domain is a group of modules fed by clock signals controlled by the same clock manager in the

PRCM module (see Figure 3-3). By gating the clocks in a clock domain, the clocks to all the modules

belonging to that clock domain can be cut to lower their active power consumption (that is, the device is

on and the clocks to the modules are dynamically switched to ACTIVE or INACTIVE [gated] state). Thus, a clock domain allows control of the dynamic power consumption of the device.

The device is partitioned into multiple clock domains and each clock domain is controlled by an associated clock manager within the PRCM module. This allows the PRCM module to activate and gate individually each device clock domain.

Figure 3-3 is an example of two clock managers: CM_a and CM_b. Each clock manager manages a clock domain. The clock domain of CM_b is composed of two clocks, a functional clock (FCLK2) and an interface clock (ICLK1), while that of CM_a consists of a clock (CLK1) that is used by the module as functional and interface clock. The clocks to Module 2 can be gated independently of the clock to Module 1, thus ensuring power savings when Module 2 is not in use. <...>

3.1.1.1.4 Clock Domain-Level Clock Management

The domain clock manager can automatically (that is, based on hardware conditions) and jointly manage the interface clocks within the clock domain. The functional clocks within the clock domain are managed through software settings.

A clock domain can switch between three possible states: ACTIVE, IDLE_TRANSITION (IDLEREQ), and INACTIVE (IDLE). Figure 3-4 shows the sleep and wake-up transitions of the clock domain between ACTIVE and INACTIVE states. <...>

Illustration from presentation.

<...>

3.1.1.2 Power Management

The PRCM module manages the switching on and off of the power supply to the device modules. To

minimize device power consumption, the power to the modules can be switched off when they are not in use. Independent power control of sections of the device lets the PRCM module turn on and off specific sections of the device without affecting other sections. Power management integration details are described in Section 3.7, Power Management Functional Description.

3.1.1.2.1 Power Domain

A power domain is a section (that is, a group of modules) of the device with an independent and dedicated power manager (see Figure 3-9). A power domain can be turned on and off without affecting other parts of the device.

To minimize device power consumption, the modules are grouped into power domains. A power domain can be split into logic and memory areas.

The memory area contains two entities:

• Memory bank: Composed of memory arrays. It is powered by a dedicated voltage rail and an

associated power switch (for example, Varray and memory array power switches).

• Memory logic: Powered by the same voltage source as the logic area of the power domain, but has its

dedicated power switch (for example, Vdd and memory logic power switches)

<...>

Illustration from presentation.

<...>

3.1.1.3 Voltage Management

The PRCM module do not provide controls over the Voltage management. All OPP changes will be

handled by Application software directly without any PRCM intervention. Voltage management integration details are described in Section 3.8, Voltage Management Functional Description.

3.1.1.3.1 Voltage Domain

A voltage domain is a section of the device supplied by a dedicated voltage source (that is, an internal

LDOs or external switch mode power supply [SMPS]). A voltage domain may or may not be controlled by the PRCM module. The voltage managers in the PRCM module is one type:

• Dynamically configurable by software to scale the domain voltage level to specific values within the

operational voltage range of the device. This is called adaptive voltage scaling (AVS).

Figure 3-11 shows a voltage domain.

By partitioning the device into independent voltage domains, different operating voltages can be assigned to the different sections of the device (that is, a group of modules or memory banks). The independent voltage control allows voltage scaling of device subsections to ensure that each module or memory bank operates at the optimized operating voltage level based on the application performance requirements.

3.1.1.3.2 Voltage Domain Management

Figure 3-12 shows the different voltage control paths available within a generic logic voltage management block to control the voltage supply to the logic voltage domains of the device.

NOTE: For more information about AVS Class 0 eFuse Voltage registers, see chapter AVS Class 0

Associated Registers in the Control Module.

<...>

3.2 PRCM Subsystem Overview

3.2.1 Introduction

The power-management framework of the device significantly reduces dynamic power consumption and static leakage current. This framework incorporates support for state-of-the-art power-management

techniques. It ensures optimal device operation with significantly reduced power consumption. The powermanagement framework (PMFW) of the device is handled by the PRCM which is a logical module composed of the following three physical submodules:

1) PRM: Handles device-level power and reset management. It also handles some clocks in the device.

This module always remains on, unless no power is supplied to the device pads.

2) CM_CORE_AON: Handles device-level clock management of the DSP1, DSP2, COREAON, CORE, IPU, L4PER, DSS, L3INIT, ISS, CAM, CUSTEFUSE, EVE1, EMU and WKUPAON power domains. This module always remains on, unless no power is supplied to the device pads.

3) CM_CORE: Handles device-level clock management of the MMR block.

The device supports the power-management techniques with the following features:

• Partitioning of the device into voltage, power, clock, and reset domains

• Domain isolation that allows any combination of domain ON/OFF states

• Clock tree with selective clock-gating conditions

• Hardware-controlled reset sequencing management

• Power, reset, and clock control hardware mechanism to manage sleep and wake-up dependencies of

the power domains

• Support for hardware-controlled autogating of module clocks

• Memory retention capability for preserving memory contents in low-power sleep mode

• DVFS support for the processor and peripherals

The PMFW interfaces with all the components of the device for power, clock, and reset management

through associated control signals. It integrates enhanced features to let the device adapt energy

consumption dynamically according to changing application and performance requirements. The

innovative hardware architecture allows a substantial reduction in leakage current.

The power-management modules are fully configurable through their L4 interface ports.

Figure 3-19 is an overview of the power-management modules and their internal connections with a

generic power domain.

3.3 PRCM Subsystem Environment

The modules of the PMFW receive the external reset, clock, and power signals. See Figure 3-19.

The following sections describe the interfaces for external clock, reset, and power sources.

3.3.1 External Clock Signals

Table 3-23 lists the external clock pins, signal names, their direction, associated module, and description of the signals. If the signal is input to the device, the module is the destination module for the signal; if the signal is an output from the device, the module is the source module of the signal.

3.3.2 External Boot Signals

The PRM receives SYSBOOT[15:0] information from external pins sys_boot[15:0]. They are used to

configure the boot mode of the device. For more information, see Chapter 25, Initialization, Section 25.2.4, Sysboot Configuration and the device Data Manual.

Table 3-24 lists the external boot configuration pins, signal names, their direction, the associated modules, description, and reset values of the signals. If the signal is input to the device, the module is the destination module for the signal; if the signal is an output from the device, the module is the source

module of the signal.

3.3.3 External Reset Signals

The PRM drives the SYS_WARM_OUT_RST reset output signal which is directly mapped as rstoutn

device pin.The PRM asserts SYS_WARM_OUT_RST output upon the assertion of any source of global

reset (warm or cold). This reset signal keeps external peripherals under reset while the device is in global reset.

Table 3-25 lists the external reset pins, signal names, their direction, associated module, and description

of the signals. If the signal is input to the device, the module is the destination module for the signal; if the signal is an output from the device, the module is the source module of the signal.

3.3.4 External Voltage Inputs

Table 3-26 lists the external voltage sources related to the PRCM module.

NOTE: Table 3-26 lists only the voltage sources that are directly managed by the PRCM module or

received by parts of the PRCM module (for example, DPLLs, LDOs, etc.). It does not give the device voltage sources not directly associated with the PRCM module. Please refer to the device Data Manual for all power pins.