1.1. EDMA integration
1.2. EDMA functional diagram
1.3. EDMA channel controller
1.4. EDMA transfer controller
Two instances of the EDMA_TPTC generate concurrent traffic on the L3_MAIN interconnect. Each TC
controller consists of the following components:
• DMA Program Register Set: Stores the context for the DMA transfer that is loaded into the active
register set when the current active register set completes. The CPU or TPCC programs the Program
Register Set, not the active register set. For typical standalone operation, the CPU programs the
Program Register while the TC services the Active register set. The Program Register set includes
ownership control such that CPU software and the EDMA stay synchronized relative to one another.
• Source Active Register Set : Stores the context (src/dst/cnt/etc) for the DMA Transfer Request (TR) in progress in the Read Controller. The Active register set is split into independent Source and
Destination, because the source interconnect controller and the distant interconnect controller operate independently of one another.
• Destination FIFO Register Set: Stores the context (src/dst/cnt/etc) for the DMA Transfer Request (TR) in progress, or pending, in the Write Controller. The pending register must allow the source controller to begin processing a new TR while the distant register set processes the previous TR.
• Channel FIFO: Temporary holding buffer for in-flight data. The read return data of the source
peripheral is stored in the Data FIFO, and then is written to the destination peripheral by the write
command/data bus.
• Read Controller/Interconnect Read Interface: The Interconnect read interface issues optimally sized read commands to the source peripheral, based on a burst size of 128 bytes and available landing space in the channel FIFO.
• Write controller/Interconnect Write interface: The local interconnect write interface issues optimally sized write commands to the destination peripheral, based on a burst size of 128 bytes and available data in the channel FIFO.
• Completion interface: sends completion codes to the EDMA_TPCC when a transfer completes and
generates interrupts and chained events in the TPCC module.
• Configuration port: Slave interface that provides read/write access to program registers and read
access to all memory-mapped TPTC registers.
When one EDMA_TPTC module is idle and receive its first TR, DMA program register set receives the
TR, where it transitions to the DMA source active set and the destination FIFO register set immediately.
The second TR (if pending from EDMA_TPCC) is loaded into the DMA program set, ensuring it can start as soon as possible when the active transfer completes. As soon as the current active set is exhausted, the TR is loaded from the DMA program register set into the DMA source active register set as well as to the appropriate entry in the destination FIFO register set.
The read controller issues read commands controlled by the rules of command fragmentation and
optimization. These are issued only when the data FIFO has space available for the data read. When
sufficient data is in the data FIFO, the write controller starts issuing a write command again following the rules for command fragmentation and optimization.
Depending on the number of entries, the read controller can process up to two or four transfer requests ahead of the destination subject to the amount of free data FIFO.
12.4.2 Types of EDMA controller Transfers
An EDMA transfer is always defined in terms of three dimensions. Figure 12-7 shows the three
dimensions used by EDMA controller transfers. These three dimensions are defined as:
• 1st Dimension or Array (A): The 1st dimension in a transfer consists of EDMA_TPCC_ABCNT_n[15:0] ACNT contiguous bytes.
• 2nd Dimension or Frame (B): The 2nd dimension in a transfer consists of
EDMA_TPCC_ABCNT_n[31:16] BCNT arrays of ACNT bytes. Each array transfer in the 2nd
dimension is separated from each other by an index programmed using bit-fields
EDMA_TPCC_BIDX_n[15:0] SBIDX or EDMA_TPCC_BIDX_n[31:16] DBIDX.
• 3rd Dimension or Block (C): The 3rd dimension in a transfer consists of CCNT frames of BCNT arrays of ACNT bytes. The Count for 3rd Dimension is defined in register EDMA_TPCC_CCNT_n[15:0] CCNT. Each transfer in the 3rd dimension is separated from the previous by an index programmed using EDMA_TPCC_CIDX_n[15:0] SCIDX or EDMA_TPCC_CIDX_n[31:16] DCIDX.
NOTE: The reference point for the index depends on the synchronization type. The amount of data
transferred upon receipt of a trigger/synchronization event is controlled by the
synchronization types (EDMA_TPCC_OPT_n[2] SYNCDIM bit). For these three dimensions,
only two synchronization types are supported: A-synchronized transfers and ABsynchronized
transfers.
12.4.2.1 A-Synchronized Transfers
In an A-synchronized transfer, each EDMA sync event initiates the transfer of the 1st dimension of
EDMA_TPCC_ABCNT_n[15:0] ACNT bytes, or one array of ACNT bytes. Each event/TR packet conveys the transfer information for one array only. Thus, BCNT × CCNT events are needed to completely service a PaRAM set.
Arrays are always separated by EDMA_TPCC_BIDX_n[15:0]SBIDX and EDMA_TPCC_BIDX_n[31:16] DBIDX, as shown in Figure 12-8, where the start address of Array N is equal to the start address of Array N – 1 plus source (SRC) or destination (DST) in EDMA_TPCC_BIDX_n register.
Frames are always separated by EDMA_TPCC_CIDX_n[15:0] SCIDX and EDMA_TPCC_CIDX_n[31:16] DCIDX. For A-synchronized transfers, after the frame is exhausted, the address is updated by adding SRCCIDX/DSTCIDX to the beginning address of the last array in the frame. As in Figure 12-8, SRCCIDX / DSTCIDX is the difference between the start of Frame 0 Array 3 to the start of Frame 1 Array 0.
Figure 12-8 shows an A-synchronized transfer of 3 (CCNT) frames of 4 (BCNT) arrays of n (ACNT) bytes. In this example, a total of 12 sync events (BCNT × CCNT) exhaust a PaRAM set. See Figure 12-8 for details on parameter set updates.
12.4.2.2 AB-Synchronized Transfers
In a AB-synchronized transfer, each EDMA sync event initiates the transfer of 2 dimensions or one frame. Each event/TR packet conveys information for one entire frame of BCNT_n arrays of ACNT_n bytes. Thus, EDMA_TPCC_CCNT_n events are needed to completely service a PaRAM set.
Arrays are always separated by EDMA_TPCC_BIDX_n[15:0] SBIDX and EDMA_TPCC_BIDX_n[31:16] DBIDX as shown in Figure 12-9. Frames are always separated by SRCCIDX and DSTCIDX.
Note that for AB-synchronized transfers, after a TR for the frame is submitted, the address update is to add EDMA_TPCC_CIDX_n[15:0] SCIDX / EDMA_TPCC_CIDX_n[31:16] DCIDX to the beginning address of the beginning array in the frame. This is different from A-synchronized transfers where the address is updated by adding SRCCIDX/DSTCIDX to the start address of the last array in the frame. See Section 12.4.3.6 Parameter Set Updates for details on parameter set updates.
Figure 12-9 shows an AB-synchronized transfer of 3 (CCNT) frames of 4 (BCNT) arrays of n (ACNT)
bytes. In this example, a total of 3 sync events (CCNT) exhaust a PaRAM set; that is, a total of 3 transfers of 4 arrays each completes the transfer.
ti tda3:
1) datasheet
2) trm
Комментариев нет:
Отправить комментарий