четверг, 27 августа 2020 г.

connect old phone lcd to arduino, rpi or stm32

1. phone lcd

1.1. arduino + cell phone lcd (usb):
1) Display for Arduino - Use Smartphone as a Monitor for Arduino https://www.youtube.com/watch?v=LXA4E7MoMxU

1.2. arduino + mobile phone lcd (spi):
1) Подключаем дисплей от сотика или мобильного телефона к Ардуино https://www.youtube.com/watch?v=ShnyOOcfbhc
2) LG KF700 cellphone TFT LCD on Arduino Mega https://www.youtube.com/watch?v=8LEjZMAbedA
3) Arduino TFT LCD Touch Screen GSM Mobile Phone https://www.youtube.com/watch?v=4-6YDET6z9E

1.3. lcd (forums):
1) Reuse old touchscren for Arduino https://forum.arduino.cc/index.php?topic=470884.0
2) using Cellphone/mobile phone display screen https://forum.pine64.org/showthread.php?tid=1923

1.4. arduino lcds:

2. parallel lcd interface, ltdc, dpi:

2.1. RPI DPI:

2.2. arm + ltdc:
1) Праздник жизни по гиковски: с ARM и TFT LCD https://habr.com/ru/post/207136/
2) Нерабочий планшет + Orange Pi https://habr.com/ru/post/396277/

2.3. stm32 + ltdc (hal):
1) STM Урок 58. System Workbench. LCD. SDIO. Часть 1 https://narodstream.ru/stm-urok-58-system-workbench-lcd-sdio-chast-1/
2) STM Урок 64. HAL. LTDC. Часть 1 https://narodstream.ru/stm-urok-64-hal-ltdc-chast-1/
3) STM32: using the LTDC display controller http://www.lucadavidian.com/2017/10/02/stm32-using-
4) Запускаем дисплей на STM32 через LTDC… на регистрах https://habr.com/ru/post/412753/
6) STM32 ОПИСАНИЕ РАБОТЫ LTDC https://hubstub.ru/stm32/171-stm32-opisanie-raboty-ltdc.html
8) Library 18- ILI9341 with LTDC on STM32F429 Discovery http://stm32f4-discovery.net/2014/06/library-18-ili9341-ltdc-stm32f429-discovery/

2.4. stm32 + ssd1963:
1) STM32 и LCD, быстрая заливка экрана https://habr.com/ru/post/278967/
2) 

2.5. stm32 + RA8876, 8080:
1) Подключение дисплея 10" ER-TFT101-1 к STM32F429 через FMC https://habr.com/ru/post/483538/

2.6. stm32 + spi lcd:
1) STM32F1хх — продолжаем лечение от ардуинозависимости при помощи LCD https://habr.com/ru/post/139384/

2.7. stm32 + lvgl library:
1) Интеграция в проект LVGL графической библиотеки для микроконтроллеров https://habr.com/ru/post/510626/
2) 


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среда, 26 августа 2020 г.

Времена года и прецессия

 Вики:

1) Времена года

2) Прецессия

3) Предварение равноденствий


Книги:

1) Хокинг, Млодинов - Кратчайшая история времени (вики)

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Байдарка "Салют-2"

Сборка/разборка:
2)  Салют 3 Нюансы сборки с новой ПВХ оболочкой https://www.youtube.com/watch?v=LkAi7ku-TeU
3) Сборка байдарки Таймень-2. Учебное пособие по туризму ИФКСиЗ САФУ 
4) Байдарка Салют: Схема сборки https://splavitsa.com/baydarka-salyut-opisanie-sxema-sborka

Вики:
1) Байдарка
2) Байдарка "Салют"
3) Сплав (туризм)

Чем заклеить шкуру, ремонт:
1) http://baydarka63.ru/taymensov.html
2) https://m.nn.ru/t/29842357
3) https://raft.2828.ru/pro/obolochki

Лея для проклейки днища:

Упаковка для байдарок:
1) (2500р.)  чехол с шнуровкой
2) (745р.) Чехол для каркаса Таймень/Салют без шнуровки http://splav-service.ru/shop/product/view/40/66.html
3) (1950р.) Рюкзак-упаковка для байдарки "два дна" http://splav-service.ru/shop/product/view/40/63.html
4) (2645р.) Рюкзак-упаковка для байдарки со шнуровкой http://splav-service.ru/shop/product/view/40/62.html
5) (1300р.) СУМКА-РЮКЗАК ДЛЯ ЛОДОК ЛОЦМАН LOCMAN https://www.decathlon.ru/ru-boat-bag-locman-id_8734304.html?fromBanner=category
7) (30$) ЧЕХОЛ ДЛЯ КАРКАСА ТАЙМЕНЬ-2 И ТАЙМЕНЬ-3 
8) (3500р.) Рюкзак-упаковка для байдарки на шнуровке http://www.qrshop.ru/upakovka-rb
9) (3040р.)Упаковка для байдарки Таймень 

Новая шкура для байдарки "Салют-2":

Сплав по реке Нерская (Куровское - пос. им. Цурюпы):
1) По речке Нерская. ПВД от пл. Куровская до Воскресенска http://x-tracks.ru/index.php/otchety/otchety-o-marshrutakh-pvd/39-po-rechke-nerskaya-pvd-ot-pl-kurovskaya-do-voskresenska
4) Разные подмосковные реки https://monitorrr.narod.ru/river.html

Чтобы весло не утонуло:
1) Как сделать разборное весло для каякинга плавучим, и как на его базе собрать канойное весло https://ergin.ru/kayaking/handmade/kak-sdelat-razbornoe-veslo-dlya-kayakinga-plavuchim-i-kak-na-ego-baze-sobrat-kanoynoe-veslo.htm

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вторник, 25 августа 2020 г.

Interrupt controllers and Control module subsystems in TDA3x

1. Interrupt subsystem

2. Control Module

2.1. IRQ_CROSSBAR

2.2. DMA_CROSSBAR

2.3. Pad configuration

Возможные значения мультиплексирования пинов приведены в datasheet к tda3 в разделе "4.2 Ball characteristics". Пример страницы с сигналами csi2 таблицы из 20-ти страниц:
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Автосимулятор в Unity3d

Ссылки:
1) UnityCar — автомобили с физикой для Unity3D https://habr.com/ru/post/130516/
2) Создание 3D гонок за 10 минут! (Unity 5) https://youtu.be/8T_KdFyYPNY
3) Создание 3D гонок на Unity 5 за 30 минут! https://youtu.be/zzg3b465yWk
4) https://www.lfs.net/

Идеи:
1) развить мем про старую мышь и молодую "когда-нибудь это будет твоим" в бесконечное движение по МКАДу
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пятница, 21 августа 2020 г.

ti gel- and cmd-files; add aem4 lib in ccs

Wiki, pdf (gel-file):
1) Creating Device Initialization GEL Files https://www.ti.com/lit/an/spraa74a/spraa74a.pdf

Funcs:
1) https://software-dl.ti.com/ccs/esd/documents/users_guide/gel/GEL_MapOff.html
2) https://software-dl.ti.com/ccs/esd/documents/users_guide/gel/GEL_MapReset.html
3) https://software-dl.ti.com/ccs/esd/documents/users_guide/gel/GEL_MapAddStr.html
4) https://software-dl.ti.com/ccs/esd/documents/users_guide/gel/GEL_LoadGel.html
5) http://software-dl.ti.com/ccs/esd/documents/users_guide_9.3.0/gel/OnTargetConnect.html

cmd-file:
1) https://software-dl.ti.com/ccs/esd/documents/sdto_cgt_Linker-Command-File-Primer.html
2) https://processors.wiki.ti.com/index.php/Linker_CMD_Files_for_CCS
3) Advanced Linker Techniques for Convenient and Efficient Memory Usage 
pragma DATA_SECTION(), CODE_SECTION():
1) Using DATA_SECTION PRAGMA With Defined Memory Section in Linker Command File
https://processors.wiki.ti.com/index.php/Placing_Variables_in_Specific_Memory_Location_-_MSP430#Using_DATA_SECTION_PRAGMA_With_Defined_Memory_Section_in_Linker_Command_File
2) ti c/c++ and assembly language compilers user guides https://www.ti.com/tool/TI-CGT#technicaldocuments
3) #pragma DATA_SECTION() expansion https://e2e.ti.com/support/tools/ccs/f/81/t/277661
4) https://stackoverflow.com/questions/1675351/typedef-struct-vs-struct-definitions
5) #pragma CODE_SECTION('.startup_code') https://e2e.ti.com/support/tools/ccs/f/81/t/41618?-pragma-CODE-SECTION-applying-to-files-groups-of-functions-

.bss:
1) https://en.wikipedia.org/wiki/.bss

add aem4 lib in ccs:
1) https://e2e.ti.com/support/processors/f/791/t/564044?CCS-Undefined-symbol-in-build-for-AM571x-M4

Error connecting to the target: (Error -1170 @ 0x0) Unable to access the DAP:
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четверг, 20 августа 2020 г.

ti tda3 power, clock management system (prcm) and digital phase-locked loop (dpll) subsystem

Power and clock management system (presentation in pdf)

3.1 Device Power Management Introduction

Power management is one of the most important design aspects of any system.

The device power-management architecture ensures maximum performance while offering versatile
power-management techniques for maximum design flexibility, depending on application requirements.

This introduction contains the following information:
• Power-management architecture building blocks for the device
• State-of-the-art power-management techniques supported by the power-management architecture of
the device

3.1.1 Device Power-Management Architecture Building Blocks

To provide a versatile architecture that supports multiple power-management techniques, the powermanagement framework is built with three levels of resource management: clock, power, and voltage. These management levels are enforced by defining the managed entities or building blocks of the powermanagement architecture, called the clock, power, and voltage domains. A domain is a group of modules or subsections of the device that share a common entity (for example, common clock source, common voltage source, or common power switch). The group forming the domain
is managed by a policy manager. For example, a clock for a clock domain is managed by a dedicated
clock manager within the power, reset, and clock management (PRCM) module. The clock manager
considers the joint clocking constraints of all the modules belonging to that clock domain (and, hence,
receiving that clock).

NOTE: In the following sections, the term <module> is used to represent the device IPs (that is,
modules or subsystems), other than the PRCM module, that receive clock, reset, or power
signals from the PRCM module.

3.1.1.1 Clock Management

The PRCM module manages the gating (that is, switching off) and enabling of the clocks to the device
modules. The clocks are managed based on the requirement constraints of the associated modules. The
following sections identify the module clock characteristics, management policy, clock domains, and clock domain management. Clock management integration details are described in Section 3.6, Clock
Management Functional Description.

3.1.1.1.1 Module Interface and Functional Clocks

Each module within the device has specific clock input characteristics requirements. Based on the
characteristics of the clocks delivered to the modules, the clocks are divided into two categories: interface clocks and functional clocks (see Figure 3-2).
The interface clocks have the following characteristics:
• They ensure proper communication between any module/subsystem and the interconnect.
• In most cases, they supply the system interconnect interface and registers of the module.
• A typical module has one interface clock, but modules with multiple interface clocks may also exist
(that is, when connected to multiple interconnect buses).
• Interface clock management is done at the device level.
• From the standpoint of the PRCM module, an interface clock is identified with an _ICLK suffix.

Functional clocks have the following characteristics:
• They supply the functional part of a module or subsystem.
• A module can have one or more functional clocks. Some functional clocks are mandatory, while others
are optional. A module needs its mandatory clock(s) to be operational. The optional clocks are used for
specific features and can be shut down without stopping the module activity (for example, the clock for
the camera).
• From the standpoint of the PRCM module, a functional clock is distributed directly to the related
modules through a dedicated clock tree. It is identified with an _FCLK suffix.

Some clocks are qualified as permanent clocks. They are functional clocks, that can stay active while the corresponding entity manages them.

3.1.1.1.2 Module-Level Clock Management

Each module in the device may also have specific clock requirements. Certain module clocks must be
active when operating in specific modes, or they may be gated. Globally, the activation and gating of the module clocks are managed by the PRCM module. Hence, the PRCM module must be aware of when to activate and when to gate the module clocks.

The PRCM module differentiates the clock-management behavior for device modules based on whether
the module can initiate transactions on the device interconnect (called master module) or it cannot initiate transactions and only responds to the transactions initiated by the master (called slave module). Thus, two hardware-based power-management protocols are used:
• Master standby protocol: Clock-management protocol between the PRCM and master modules
• Slave idle protocol: Clock-management protocol between the PRCM and slave modules
<...>

Master module STANDBY and slave module IDLE protocols (from presentation).


3.1.1.1.3 Clock Domain

A clock domain is a group of modules fed by clock signals controlled by the same clock manager in the
PRCM module (see Figure 3-3). By gating the clocks in a clock domain, the clocks to all the modules
belonging to that clock domain can be cut to lower their active power consumption (that is, the device is
on and the clocks to the modules are dynamically switched to ACTIVE or INACTIVE [gated] state). Thus, a clock domain allows control of the dynamic power consumption of the device.

The device is partitioned into multiple clock domains and each clock domain is controlled by an associated clock manager within the PRCM module. This allows the PRCM module to activate and gate individually each device clock domain.
Figure 3-3 is an example of two clock managers: CM_a and CM_b. Each clock manager manages a clock domain. The clock domain of CM_b is composed of two clocks, a functional clock (FCLK2) and an interface clock (ICLK1), while that of CM_a consists of a clock (CLK1) that is used by the module as functional and interface clock. The clocks to Module 2 can be gated independently of the clock to Module 1, thus ensuring power savings when Module 2 is not in use. <...>

3.1.1.1.4 Clock Domain-Level Clock Management

The domain clock manager can automatically (that is, based on hardware conditions) and jointly manage the interface clocks within the clock domain. The functional clocks within the clock domain are managed through software settings.

A clock domain can switch between three possible states: ACTIVE, IDLE_TRANSITION (IDLEREQ), and INACTIVE (IDLE). Figure 3-4 shows the sleep and wake-up transitions of the clock domain between ACTIVE and INACTIVE states. <...>

Illustration from presentation. 

<...>

3.1.1.2 Power Management

The PRCM module manages the switching on and off of the power supply to the device modules. To
minimize device power consumption, the power to the modules can be switched off when they are not in use. Independent power control of sections of the device lets the PRCM module turn on and off specific sections of the device without affecting other sections. Power management integration details are described in Section 3.7, Power Management Functional Description.

3.1.1.2.1 Power Domain

A power domain is a section (that is, a group of modules) of the device with an independent and dedicated power manager (see Figure 3-9). A power domain can be turned on and off without affecting other parts of the device.
To minimize device power consumption, the modules are grouped into power domains. A power domain can be split into logic and memory areas.

The memory area contains two entities:
• Memory bank: Composed of memory arrays. It is powered by a dedicated voltage rail and an
associated power switch (for example, Varray and memory array power switches).
• Memory logic: Powered by the same voltage source as the logic area of the power domain, but has its
dedicated power switch (for example, Vdd and memory logic power switches)
<...>
Illustration from presentation.
<...>

3.1.1.3 Voltage Management

The PRCM module do not provide controls over the Voltage management. All OPP changes will be
handled by Application software directly without any PRCM intervention. Voltage management integration details are described in Section 3.8, Voltage Management Functional Description.

3.1.1.3.1 Voltage Domain

A voltage domain is a section of the device supplied by a dedicated voltage source (that is, an internal
LDOs or external switch mode power supply [SMPS]). A voltage domain may or may not be controlled by the PRCM module. The voltage managers in the PRCM module is one type:
• Dynamically configurable by software to scale the domain voltage level to specific values within the
operational voltage range of the device. This is called adaptive voltage scaling (AVS).

Figure 3-11 shows a voltage domain.
By partitioning the device into independent voltage domains, different operating voltages can be assigned to the different sections of the device (that is, a group of modules or memory banks). The independent voltage control allows voltage scaling of device subsections to ensure that each module or memory bank operates at the optimized operating voltage level based on the application performance requirements.

3.1.1.3.2 Voltage Domain Management

Figure 3-12 shows the different voltage control paths available within a generic logic voltage management block to control the voltage supply to the logic voltage domains of the device.
NOTE: For more information about AVS Class 0 eFuse Voltage registers, see chapter AVS Class 0
Associated Registers in the Control Module.
<...>

3.2 PRCM Subsystem Overview

3.2.1 Introduction

The power-management framework of the device significantly reduces dynamic power consumption and static leakage current. This framework incorporates support for state-of-the-art power-management
techniques. It ensures optimal device operation with significantly reduced power consumption. The powermanagement framework (PMFW) of the device is handled by the PRCM which is a logical module composed of the following three physical submodules:

1) PRM: Handles device-level power and reset management. It also handles some clocks in the device.
This module always remains on, unless no power is supplied to the device pads.

2) CM_CORE_AON: Handles device-level clock management of the DSP1, DSP2, COREAON, CORE, IPU, L4PER, DSS, L3INIT, ISS, CAM, CUSTEFUSE, EVE1, EMU and WKUPAON power domains. This module always remains on, unless no power is supplied to the device pads.

3) CM_CORE: Handles device-level clock management of the MMR block.

The device supports the power-management techniques with the following features:
• Partitioning of the device into voltage, power, clock, and reset domains
• Domain isolation that allows any combination of domain ON/OFF states
• Clock tree with selective clock-gating conditions
• Hardware-controlled reset sequencing management
• Power, reset, and clock control hardware mechanism to manage sleep and wake-up dependencies of
the power domains
• Support for hardware-controlled autogating of module clocks
• Memory retention capability for preserving memory contents in low-power sleep mode
• DVFS support for the processor and peripherals

The PMFW interfaces with all the components of the device for power, clock, and reset management
through associated control signals. It integrates enhanced features to let the device adapt energy
consumption dynamically according to changing application and performance requirements. The
innovative hardware architecture allows a substantial reduction in leakage current.
The power-management modules are fully configurable through their L4 interface ports.

Figure 3-19 is an overview of the power-management modules and their internal connections with a
generic power domain.
3.3 PRCM Subsystem Environment

The modules of the PMFW receive the external reset, clock, and power signals. See Figure 3-19.
The following sections describe the interfaces for external clock, reset, and power sources.

3.3.1 External Clock Signals

Table 3-23 lists the external clock pins, signal names, their direction, associated module, and description of the signals. If the signal is input to the device, the module is the destination module for the signal; if the signal is an output from the device, the module is the source module of the signal.

3.3.2 External Boot Signals

The PRM receives SYSBOOT[15:0] information from external pins sys_boot[15:0]. They are used to
configure the boot mode of the device. For more information, see Chapter 25, Initialization, Section 25.2.4, Sysboot Configuration and the device Data Manual.

Table 3-24 lists the external boot configuration pins, signal names, their direction, the associated modules, description, and reset values of the signals. If the signal is input to the device, the module is the destination module for the signal; if the signal is an output from the device, the module is the source
module of the signal.

3.3.3 External Reset Signals

The PRM drives the SYS_WARM_OUT_RST reset output signal which is directly mapped as rstoutn
device pin.The PRM asserts SYS_WARM_OUT_RST output upon the assertion of any source of global
reset (warm or cold). This reset signal keeps external peripherals under reset while the device is in global reset.

Table 3-25 lists the external reset pins, signal names, their direction, associated module, and description
of the signals. If the signal is input to the device, the module is the destination module for the signal; if the signal is an output from the device, the module is the source module of the signal.

3.3.4 External Voltage Inputs

Table 3-26 lists the external voltage sources related to the PRCM module.

NOTE: Table 3-26 lists only the voltage sources that are directly managed by the PRCM module or
received by parts of the PRCM module (for example, DPLLs, LDOs, etc.). It does not give the device voltage sources not directly associated with the PRCM module. Please refer to the device Data Manual for all power pins.






1.6. Clock manager.








"CTRLCLK of CAMERARX is driven by FUNC_96M_FCLK coming from DPLL_PER. This implies either of the following modules has to be enabled: I2C1 or I2C2."

2. digital phase-locked loop (dpll) subsystem.

"The DPLL has three input clocks:
• REF_CLK: Used to generate the synthesized clock but can also be used as the bypass clock for some
outputs of the DPLL whenever the DPLL enters bypass mode. It is mandatory for the DPLL clock
synthesis.
• BYP_CLK_M2: Selectable bypass clock for the output of an M2 post-divider (optional)
• BYP_CLK_M3: Selectable bypass clock for the output of an M3 post-divider (optional)
The DPLL provides the bypass clock used by HSDIVIDER: BYP_CLK_Hmn, which is output by the
multiplexer between the BYP_CLK_M2 and REF_CLK clock signals.

The DPLL can be programmed to be locked at any frequency given by one of the following equation:
Fdpll = Fref ×2 ×M / (N + 1)

Where:
• Fdpll is the DPLL lock frequency.
• Fref is the REF_CLK frequency. Fref is also known as CLKINP.
• M is the software-configured multiplication ratio binary value.
• N is the software-configured division ratio binary value.

NOTE: It is preferred to minimize the value for N parameter (it minimizes lock time and jitter)."


For example, for CM_CLKSEL_DPLL_GMAC: 
1) M (multiplier) = CM_CLKSEL_DPLL_GMAC.DPLL_MULT; 
2) N (divider) = CM_CLKSEL_DPLL_GMAC.DPLL_DIV.

For example, REF_CLK=Fref = 20 MHz. M = 75. N = 1.

Fdpll = ( 20 MHz * 2 * 75 ) / (1 + 1) = (3000 / 2) MHz = 1500 MHz = 1,5 GHz








ti tda3:
1) trm

power source lp873x:
1) user's guide
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среда, 19 августа 2020 г.

Как пожарить лисички с луком

 Ссылки:

1) https://cookpad.com/ru/recipes/4176807-lisichki-zharienyie-s-lukom

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Ультразвуковая левитация

 Arduino + ultrasonic sensor HC-SR04:

1) Легкодоступная левитация в ультразвуке https://habr.com/ru/post/432934/

2) Micro Ultrasonic Levitator https://makezine.com/projects/micro-ultrasonic-levitator/


Ультразвук, левитация:

1) Ультразвук

2) Ультразвуковая дефектоскопия

3) Акустическая левитация 

https://mipt.ru/upload/medialibrary/4b5/yurko_maksim_acoustic_levitation.pdf

4) Ультразвуковая волшебная палочка https://nkj.ru/news/25621/

5) Физики научились заставлять большие предметы летать с помощью звука https://www.popmech.ru/science/256352-fiziki-nauchilis-levitirovat-bolshie-predmety-s-pomoshchyu-zvuka/

6) Побит рекорд звуковой левитации шариков https://nplus1.ru/news/2016/08/15/levitation

7) Акустическая левитация позволила создать псевдоголографический дисплей https://nplus1.ru/news/2019/10/23/leviprops

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stm32 phase locked loop (pll) (регистр rcc)

Настойка регистра RCC:
1) STM Урок 166. CMSIS. STM32F1. RCC. Часть 1 https://narodstream.ru/stm-urok-166-cmsis-stm32f1-rcc-chast-1/
2) STM32F407, разрешение тактирования периферийных устройств http://microsin.net/programming/arm/stm32f407-peripheral-clock-enable.html
3) STM32F407: инструментарий для конфигурирования тактовых частот http://microsin.net/programming/arm/clock-configuration-tool-for-stm32f40xx.html
4) ARM. Учебный курс. Тактовый генератор STM32 http://easyelectronics.ru/arm-uchebnyj-kurs-taktovyj-generator-stm32.html
5) STM32: Clock Security System https://habr.com/ru/post/140761/
6) Разбираемся с тактированием МК https://stm32.chrns.com/post/149086504894/clocksystem
7) Программирование STM32. Часть 4: Настройка RCC http://dimoon.ru/obuchalka/stm32f1/uroki-stm32f103-chast-4-nastroyka-rcc.html
8) STM32 ТАКТИРОВАНИЕ https://hubstub.ru/stm32/140-stm32-taktirovanie.html
9) Программирование STM32. Часть 2. Система тактирования STM32 https://ergoz.ru/programmirovanie-stm32-chast-2-sistema-taktirovaniya-stm32/

PLL (phase-locked loop):
1) https://en.wikipedia.org/wiki/Phase-locked_loop
2) ФАПЧ
3) http://dsplib.ru/content/dpll/dpll.html
4) http://www.dsplib.ru/content/pll/pll.html
5) https://www.analog.com/en/analog-dialogue/articles/phase-locked-loop-pll-fundamentals.html
6) https://www.analog.com/en/products/rf-microwave/phase-locked-loop.html
7) Introduction to phase-locked loop system modeling https://www.ti.com/lit/an/slyt169/slyt169.pdf

Кварцевый тактовый генератор:
1) Кварцевый резонатор
2) Генератор тактовых импульсов
3) Генератор сигналов
4) Кварцевый генератор
5) Кварц
6) Автогенератор
7) Свойства кварцевого резонатора
8) Пьезоэлектрики
9) Пьезоэлектрический эффект

Собственная частота колебания твердого тела, резонанс:
1) Резонанс
2) https://en.wikipedia.org/wiki/Natural_frequency
3) Нормальные колебания (https://en.wikipedia.org/wiki/Normal_mode)
4) Natural Frequency and Resonance https://www.youtube.com/watch?v=X-hjeVc127I
5) Physics - 26.3 Natural Frequency and Resonance https://www.youtube.com/watch?v=XwlZBJIp1AA
6) Natural Frequency and Resonance https://community.sw.siemens.com/s/article/Natural-Frequency-and-Resonance
7) What Is Natural Frequency? https://www.thoughtco.com/natural-frequency-4570958
8) Natural frequency: The good, the bad and the catastrophic https://blog.teufelaudio.com/natural-frequency/

Физика колебаний:
1) А.Н. Паршаков - Физика колебаний https://pstu.ru/files/file/oksana/2011/fakultety_i_kafedry/fpmm/prikladnaya_fizika/informacionnye_resursy/parshakov_fizika_kolebaniy_korr_.pdf
2) Комментарии к лекциям по физике Тема: Вынужденные колебания осциллятора при синусоидальном внешнем воздействии http://butikov.faculty.ifmo.ru/Lectures/Oscillations-2.pdf
3) С.Я.БЕКШАЕВ, В.М.ФОМИН - ОСНОВЫ ТЕОРИИ КОЛЕБАНИЙ (учебное пособие для студентов направлений «Строительство», «Гидротехника (Водные ресурсы), «Машиностроение») http://eqworld.ipmnet.ru/ru/library/books/BekshaevFomin2013ru.pdf
4) РЕЗОНАНС В ПРИРОДЕ. Резонанс. Фейнмановские лекции по физике https://fizika-student.ru/rezonans-v-prirode-rezonans-fejnmanovskie-lekcii-po-fizike.html

stm32 и гистерезис:
1) Гистерезис
2) Управляем генератором или борьба с АЦП в STM32F030 https://habr.com/ru/post/448202/
3) Датчик освещённости https://themagicsmoke.ru/courses/stm32/light_sensor.html
4) STM32 - энергосбережение и WatchDog https://istarik.ru/blog/stm32/117.html
5) Схема сброса в stm32 cortex-m3 (предусмотрен гистерезис) 
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Как работает

Как работает:

1) Сим-карта https://www.youtube.com/watch?v=oMUIGqjvcKQ

2) Ключ от домофона https://www.youtube.com/watch?v=PxtNRoc_7J8

3) Скрытые функции батарейки https://www.youtube.com/watch?v=JM6t5x_nRGE

4) 

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суббота, 15 августа 2020 г.

Как сделать домашний творог из молока

 Ссылки:

1) https://vkusno-i-prosto.ru/receipt/domashnij-tvorog-iz-moloka/

2) https://lifehacker.ru/kak-sdelat-domashnij-tvorog/

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среда, 12 августа 2020 г.

ti vision sdk and sys/bios (ti-rtos)

ti vision sdk 03_06_00_00 download (03_08_00_00):
1. Описание сборки  исходников vision sdk под винду 10/7 vision sdk 03_06_00_00 здесь, инструкция по редактированию мэйкфайлов здесь. 

Прописываем в винде в переменную окружения PATH путь к gmake: C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\ti_components\os_tools\windows\xdctools_3_32_01_22_core в соответствии с второй частью руководства.

1.1. Собираем статические либы для ipu0 arm-cortex-m4 конфигурацию tda3xx_evm_bios_iss в debug.

В соответствии с упомянутым руководством изменяем в файле C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\vision_sdk\build\Rules.make:
- строчку MAKEAPPNAME?=apps
- строчку MAKECONFIG?=tda3xx_evm_bios_iss
- строчку BUILD_OS ?= Windows_NT

Меняем в файле 
C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\vision_sdk\apps\configs\tda3xx_evm_bios_iss\cfg.mk:
- строчку PROFILE=debug

Запускаем терминал, переходим в папку C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\vision_sdk\build и запускаем, чтобы подтвердить, что выбрана правильная конфигурация сборки:

gmake showconfig

Получаем следующий вывод:

C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\vision_sdk\build>gmake -s -j showconf
ig
#
# Build Config is [ tda3xx_evm_bios_iss ]
# Build Config file is @ C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/c
onfigs/tda3xx_evm_bios_iss/cfg.mk
# Build Config .h file is @ C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/vision_sd
k/links_fw/include/config/apps/tda3xx_evm_bios_iss/system_cfg.h
# Build CPUs is @ ipu1_0
#
# CPUs included in application,
# PROC_IPU1_0_INCLUDE=yes
# PROC_IPU1_1_INCLUDE=no
# PROC_IPU2_INCLUDE=no
# PROC_DSP1_INCLUDE=no
# PROC_DSP2_INCLUDE=no
# PROC_EVE1_INCLUDE=no
# PROC_EVE2_INCLUDE=no
# PROC_EVE3_INCLUDE=no
# PROC_EVE4_INCLUDE=no
# PROC_A15_0_INCLUDE=no
#
# Platform config,
# VSDK_BOARD_TYPE=TDA3XX_EVM [options: TDA2XX_EVM TDA2EX_EVM TDA3XX_EVM TDA3XX_R
VP TDA2XX_RVP]
# PLATFORM=tda3xx-evm
# DUAL_A15_SMP_BIOS=no
# IPU1_SMP_BIOS=no
# DDR_MEM=DDR_MEM_512M [options: DDR_MEM_128M DDR_MEM_512M DDR_MEM_1024M]
# EMIFMODE=SINGLE_EMIF_512MB [options: SINGLE_EMIF_512MB SINGLE_EMIF_1GB ref bui
ld_pdk.mk]
# NDK_PROC_TO_USE=none [options: a15_0 ipu1_0 ipu1_1 ipu2 none]
# NSP_TFDTP_INCLUDE=no [options: yes no]
# TDA2EX_ETHSRV_BOARD=no [options: yes no]
# FATFS_PROC_TO_USE=ipu1_0 [options: ipu1_0 none]
# RADAR_BOARD=none [options: TDA3XX_AR12_ALPS TDA3XX_AR12_VIB_DAB_BOOSTER TDA3XX
_RADAR_RVP none]
#
# Build config,
# BUILD_OS=Windows_NT [options: Windows_NT Linux]
# BUILD_DEPENDENCY_ALWAYS=no
# BUILD_ALGORITHMS=no
# BUILD_INFOADAS=no
# PROFILE=debug [options: debug release]
# KW_BUILD=no
# CPLUSPLUS_BUILD=no
# IPU_PRIMARY_CORE=ipu1_0 [options: ipu1_0 ipu2]
# IPU_SECONDARY_CORE=ipu2 [options: ipu1_0 ipu2]
# A15_TARGET_OS=Bios [options: Bios Linux Qnx]
# BSP_STW_PACKAGE_SELECT=all [options: all vps-iss-dss-only vps-vip-vpe]
#
# Safety Module config,
# RTI_INCLUDE=no
# ECC_FFI_INCLUDE=no
# DCC_ESM_INCLUDE=no
#
# Video Module config,
# IVAHD_INCLUDE=no
# VPE_INCLUDE=no
# CAL_INCLUDE=yes
# ISS_INCLUDE=yes
# ISS_ENABLE_DEBUG_TAPS=no
# WDR_LDC_INCLUDE=yes
# DSS_INCLUDE=yes
#
# Open Compute config,
# OPENCL_INCLUDE=no
# TARGET_ROOTDIR=C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/apps/src/
rtos/opencl
# ENABLE_OPENCV=no
# ENABLE_OPENCV_TESTS=no
# OPENVX_INCLUDE=no
#
# Log config,
# ENABLE_UART_LOG=yes
# ENABLE_NETWORK_LOG=no
# ENABLE_CCS_LOG=no
# CIO_REDIRECT=yes
#
# IPC config,
# WORKQ_INCLUDE=no
# IPC_LIB_INCLUDE=no
#
# AUTOSAR_APP=no
#
# Surround View config,
# SRV_FAST_BOOT_INCLUDE=no
#
# Other Module config,
# AVB_INCLUDE=no
# DCAN_INCLUDE=no
# RADAR_ONLY=no
# CPU_IDLE_ENABLED=no
# FAST_BOOT_INCLUDE=no
# DATA_VIS_INCLUDE=no
# HS_DEVICE=no
# ULTRASONIC_INCLUDE=no
# PGA450=
# PGA460=
# ENABLE_ALL_DEPTH=
#
# Linux config,
# DEFAULT_UBOOT_CONFIG=dra7xx_evm_vision_config
# DEFAULT_KERNEL_CONFIG=ti_sdk_dra7x_release_defconfig
# DEFAULT_DTB=dra7-evm-infoadas.dtb
# CMEM_INCLUDE=no
# IPUMM_INCLUDE=no
# IPU1_EVELOADER_INCLUDE=no
# ROBUST_RVC_INCLUDE=no
# BUILD_ADAM_CAR=no
#
# Alg plugins included in build,
# ALG_sceneobstruction ALG_iss_aewb
#
# Use-cases included in build,
# UC_iss_capture_isp_simcop_display
#
#
# CPUs that are NOT required but included in config [ tda3xx_evm_bios_iss ],
#
#
# CPUs that are required but not included in config [ tda3xx_evm_bios_iss ],
#
#
# Edit C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/apps/configs/tda3xx
_evm_bios_iss/cfg.mk to include or exclude CPUs in an application
#

Варианты сборки получаем выполнением команды gmake help:

C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\vision_sdk\build>gmake help
#
# Vision SDK Build System
#
# Basic targets,
# gmake -s -j showconfig // Show current build config
# gmake -s -j depend // Generate config, Build PDK, EDMA3LLD, touch dependa
nt files
# gmake -s -j // Incremental build, build vision sdk lib, alg_plugin
s, apps, binaries
# gmake -s -j appimage // Generate bootable application image
# gmake -s -j sbl // Generate SBL including SBL firmware for all boot mo
des
#
# Advanced targets,
# gmake -s -j makeconfig // Generate config related files
# gmake -s -j pdk // Build PDK
# gmake -s -j edma3lld // Build EDMA3LLD
# gmake -s -j algorithmslib // Build Algorithm libraries
# gmake -s -j links_fw_libs // Build Vision SDK framework library
# gmake -s -j vision_sdk_alg_plugins // Build Vision SDK algo plugins
# gmake -s -j apps // Build Vision SDK BIOS applications binar
ies
#
# Linux related targets,
# gmake -s -j linux // Build linux kernel, uboot, sgx drivers
# gmake -s -j linux_install // Install kernel, uboot, sgx files into filesys
tem
# gmake -s -j vision_sdk_linux // Build Vision SDK linux side library and binar
ies
# gmake -s -j uboot // Build uboot
# gmake -s -j kernel // Build kernel
# gmake -s -j sgx // Build sgx drivers
#
# Qnx related targets,
# gmake -s -j vision_sdk_qnx // Build Vision SDK qnx side library and binaries
#

Запускаем сборку зависимостей (Incremental build, build vision sdk lib, alg_plugin
s, apps, binaries):
gmake

Получаем при сборке следующее сообщение: "C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/apps/src/rtos/draw2d/draw
2d_font_bmp.c", line 61: fatal error: cannot open source file "system_cfg.h"
1 catastrophic error detected in the compilation of "C:/ti_830/PROCESSOR_SDK_VIS
ION_03_06_00_00/vision_sdk/apps/src/rtos/draw2d/draw2d_font_bmp.c".
Compilation terminated.

Этого файла нет в vision sdk, просто комментим в файле draw2d_font_bmp.c включение:

//#include <system_cfg.h>
#include <src/rtos/draw2d/draw2d_priv.h>

Также поступаем с файлами:
"C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\vision_sdk\apps\src\rtos\radar\src\alg_plugins\alg_fxns\common\alg_functions.c",
"C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/apps/src/rtos/radar/inclu
de/common/chains_radar.h",
"C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/apps/src/rtos/radar/inclu
de/common/chains_radar_cfg.h",
"C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/apps/src/rtos/common/chains_main_bios.c",
"C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/apps/src/rtos/common/chains_main_bios_stereo.c",
"C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/apps/src/rtos/common/chains_main_bios_avb.c",
"C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/apps/src/rtos/common/chains_main_bios_multi_cam.c",
"C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/apps/src/rtos/common/chains_main_bios_single_cam.c",
"C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/apps/src/rtos/common/chains_main_bios_iss.c",
"C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/apps/src/rtos/common/chains_main_bios_opencl.c",
"C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/apps/src/rtos/common/chains_main_bios_misc.c",
"C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/apps/src/rtos/common/chains_main_bios_vision.c",
"C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/apps/src/rtos/common/chains_main_bios_rsvp.c",
"C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/apps/src/rtos/common/chains_main_bios_tidl.c",
"C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/apps/src/rtos/common/chains_main_bios_cam_radar_combo.c",
"C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/apps/src/rtos/modules/grpxSrc/grpxSrcLink_tsk.c",
"C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/apps/src/rtos/modules/grpxSrc/grpxSrcLink_Tda3x2D3DSv_layout.c".

Также исправления:

1) gmake C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/vision_sdk/binaries/apps/tda3xx_evm_bios_iss/lib/tda3xx-evm/ipu1_0/debug/links_common_system.aem4
...
"system_initDeinitLinks.c", line 110: fatal error: cannot open source file "linksInclude_ipu1_0.h"
1 catastrophic error detected in the compilation of "system_initDeinitLinks.c".
Compilation terminated.

Комментим в файле C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\vision_sdk\links_fw\src\rtos\links_common\system\system_initDeinitLinks.c строчку:

#ifdef BUILD_M4_0
    //#include <linksInclude_ipu1_0.h>
#endif

2) C:/ti_830/PROCESSOR_SDK_VISION_03_06_00_00/ti_components/cg_tools/windows/ti-cgt-arm_16.9.2.LTS/bin/armcl - ... algorithmLink_cfg.c
"algorithmLink_cfg.c", line 79: fatal error: cannot open source file "system_cfg.h"

Комментим в файле C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\vision_sdk\links_fw\src\rtos\links_common\algorithm\algorithmLink_cfg.c строчку

//#include <system_cfg.h>

3) # Compiling tda3xx-evm:ipu1_0:debug:utils_common: network_tfdtp_api.c

C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\vision_sdk\links_fw\src\rtos\utils_common\src\network_tfdtp_api.c

//#include <system_cfg.h>

В итоге в папке 
C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\vision_sdk\binaries\apps\tda3xx_evm_bios_iss
получаем собранные статические либы.

1.2. Собираем статические либы для всех ядер tda3x для конфигурации tda3xx_evm_bios_all в release.

В соответствии с упомянутым руководством изменяем в файле C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\vision_sdk\build\Rules.make:
- строчку MAKEAPPNAME?=apps
- строчку MAKECONFIG?=tda3xx_evm_bios_all

Меняем в файле 
C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\vision_sdk\apps\configs\tda3xx_evm_bios_all\cfg.mk:
- строчку PROFILE=debug

Запускаем сборку зависимостей :
gmake

1.3. Собираем pdk:

gmake -s -j pdk



В числе прочего были собраны либы pdk (gmake pdk - запускает сборку либ отдельно). Они находятся в подпапках 
C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\ti_components\drivers\pdk_01_10_02_07\packages\ti\drv, а также в папках:
1) C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\ti_components\drivers\pdk_01_10_02_07\packages\ti\csl\lib\tda3xx\m4\debug
2) C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\ti_components\drivers\pdk_01_10_02_07\packages\ti\diag\lib\tda3xx\m4\debug

Меня интересуют проект vps, вернее, примеры к нему. Путь к статическим либам:
1) C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\ti_components\drivers\pdk_01_10_02_07\packages\ti\drv\vps\lib\tda3xx\ipu1_0\debug\:
- vps_osal_baremetal.aem4
2) C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\ti_components\drivers\pdk_01_10_02_07\packages\ti\drv\vps\lib\tda3xx\m4\debug\:
- vps_common.aem4
- vps_devices.aem4
- vps_osal_baremetal.aem4
- vps_platforms.aem4
- vpsdrv.aem4
- vpsdrv_baremetal.aem4
- vpslib.aem4
3) C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\ti_components\drivers\pdk_01_10_02_07\packages\ti\drv\vps\lib\tda3xx-evm\m4\debug:
- vps_boards.aem4
- vps_examples_utility.aem4



2. Сборка лежащего внутри sysbios 6_46_06_00.

Инструкция по сборке с помощью прилагающихся мэйфайлов описана в разделе A официальной доки TI-RTOS kernel (SYS/BIOS) user's guide здесь.

Копируем папку, содержащую sysbios, в другую (у меня C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\ti_components\os_tools\copy_to_rebuild_bios_6_46_06_00); оставим основную папку нетронутой, все действия будем производить с бэкапом.

Редактируем файл bios.mak, изменим следующие строчки:

XDC_INSTALL_DIR ?= C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\ti_components\os_tools\windows\xdctools_3_32_01_22_core

ti.targets.C674 ?= C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\ti_components\cg_tools\windows\ti-cgt-c6000_8.2.4

ti.targets.arm.elf.M4 = C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\ti_components\cg_tools\windows\ti-cgt-arm_16.9.2.LTS

gnu.targets.arm.M4 ?= C:\ti_830\ccsv8\tools\compiler\gcc-arm-none-eabi-7-2017-q4-major-win32

XDCOPTIONS=v

Сохраним изменения в файле. Запускаем сначала очистку, затем сборку:

cd C:\ti_830\PROCESSOR_SDK_VISION_03_06_00_00\ti_components\os_tools\copy_to_rebuild_bios_6_46_06_00
gmake -f bios.mak clean
gmake -f bios.mak


ti-rtos sys/bios:
2) TI-RTOS Kernel (SYS/BIOS) User's Guide https://www.ti.com/lit/ug/spruex3v/spruex3v.pdf

arm cortex-m4:
tda pdk:
1) (!) PDK/PDK Application Notes Video Driver Porting
3) (!) PDK/PDK VPS FVID2 User Guide 
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